Senior Advanced Verification ASIC FPGA Engineer

ACARA Solutions and our client in Scottsdale, AZ have a contract to direct hire position available

Senior Advanced Verification ASIC FPGA Engineer

• Lead the architecture definition, system simulation, and detailed design approach for ASIC/FPGA development projects.
• Define module interfaces and ensure all aspects of device design and simulation are meticulously addressed.
• Create comprehensive test and simulation plans that establish functional criteria for device validation.
• Verify test results, analyze performance, and ensure optimal functionality.
• Review vendor capabilities, foundry technologies, device libraries, and simulation tools to ensure alignment with project requirements.
• Contribute to the creation and maintenance of essential work products, including plans, specifications, and design documentation, for internal teams and external customers.
• Present design requirements, concepts, decisions, and results to internal management, cross-functional teams, and customers.
• Support technical subcontract management, including developing Statements of Work (SOW), proposal evaluation, source selection, technical oversight, and work product evaluation and acceptance.
• Assess and review vendor capabilities to ensure support for product development.
• Apply a strong understanding of defined organizational processes throughout the program or project lifecycle.
• Contribute to the continuous improvement of ASIC/FPGA organizational processes and methodologies.
• Ensure adherence to standards, procedures, and tools throughout the development lifecycle to generate high-quality engineering products.
• Lead the research and analysis of customer design proposals, specifications, and manuals to determine design feasibility.
• Select components and equipment based on detailed analysis of specifications and reliability.
• Contribute to technical approaches for small-scale proposals and projects.
• Provide leadership, mentorship, and direction to junior engineers.
• Lead technical tasks for small teams or projects and exercise autonomy in determining technical objectives.
• Guide the successful completion of major programs and projects while maintaining high technical standards.

• Proven expertise in ASIC/FPGA design and development.
• Strong experience with design, simulation, verification, and test planning.
• Familiarity with vendor management and technical subcontracting.
• Experience leading small teams and providing technical guidance.
• Excellent communication skills for both technical and non-technical audiences.

• Bachelor's Degree in Electrical or Computer Engineering or Engineering or Science or Mathematics
• Minimum of 8 years experience in System Verilog object-oriented programming and the Universal Verification Methodology (UVM)
• Minimum of 8 years experience with predictive testbench components, functional coverage and assertions
• Minimum of 8 years experience with constrained random testing
• Minimum of 8 years experience with the Register Abstraction Layer
• Minimum of 8 years experience in verifying FPGAs or ASICs
• Minimum of 8 years experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or in a Linux Environment
• Minimum of 8 years experience with requirements-based verification, requirement tracing, and developing requirement verification strategies
• Minimum of 8 years experience with scripting languages such as Linus shell scripts, TCL, Python
• Minimum of 8 years experience with using Formal Verification tools, code coverage, writing waivers
• Minimum of 8 years experience using and developing UVM agents, bus functional models
• Minimum of 8 years experience in UVM Testbench Architectures
• Minimum of 8 years experience in Microsoft Office applications

• Master's Degree
• Familiarity with the following
  1. Questa Verification IP (QVIP)
  2. Developing UVM test benches for designs implemented in Xilinx devices with Xilinx IP and SoCs
  3. AXI protocols, PCIe, Space Wire, and Ethernet interfaces
  4. DSP functions and common signal-processing components
  5. Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration.
  6. Continuous Integration features of GitLab
• Understand different types of coverage, usage of cover classes, cover points
• Contributes to the development of new theories and methods in ASIC/FPGA engineering
• Excellent understanding of ASIC/FPGA engineering processes
• Excellent awareness of business objectives and Engineering's role in achieving
• Excellent written and verbal communication skills
• Ability to think creatively
• Ability to multi-task
• Excellent skill in communicating issues, impacts, and corrective actions
• Excellent ability to recognize and clearly report information relevant to sound engineering design
• Excellent understanding of basic project leadership principles, including SPI/CPI, Earned Value, Cost Account Management (CAM), and Statistical Process Controls
• Provides resolution to problems to a diverse range of complex problems which require the use of ingenuity and creativity
• Frequent contact with managers within and outside of Engineering
• Frequent contact with project teams across the company
• Frequent contact with external customers and vendors
• Occasional contact with Business Development.

Additional Information:

• Upon offer of employment, the individual will be subject to a background check and a drug screen.
• Active Secret DoD Clearance
• In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire.
• Under the International Traffic in Arms Regulations (ITAR), all employees assigned to this client must provide documentation verifying their status as a 'U.S. Person,' as defined in ITAR clause 120.15. A U.S. Person is a protected individual under the anti-discrimination provisions of U.S. immigration laws.