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Physical Verification CAD Intern - Master's Degree

Marvell Semiconductor, Inc.
paid holidays, sick time
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Sep 18, 2025

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Develop physical verification methodology for advance nodes and 3DIC package, supporting Calibre and ICV-based physical verification tools. Provide user support for Design Rule Checking (DRC) and Layout Versus Schematic (LVS) debugging to streamline the overall verification flow. Automate and enhance physical verification processes for the internal design tools team. Support tape-out activities and manage foundry interfaces related to physical verification and SoC integration CAD flows. Create and maintain validation procedures, user documentation, and guides for PV workflows. Responsibilities also include using full-custom layout tools to review verification results and develop validation test cases.

What You Can Expect

  • Develop and maintain leading-edge Physical Verification and Extraction flows addressing the needs of Marvell's various Business Units
  • Contribute to the deployment and support of these flows
  • Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform
  • Keep up with process and tool evolutions

What We're Looking For

  • Currently enrolled in a Master's degree program in Computer Science, Electrical Engineering, or a closely related field.
  • Academic or project-based experience in CAD and EDA tool development, ideally with exposure to the semiconductor design workflows.
  • Familiarity with induscty-standard EDA tools and methodologies used in digital and analog IC design, verification, and physical implementation. Exposure to tools such as Siemens, Synopsys, Cadence, and scripting languages including Python, Tcl, Perl, as well as Siemens Calibre SVRF/TVF and Synopsys ICV, is preferred.
  • Foundational understanding of the IC design flow, including front-end processes and back-end tages.
  • Strong analytical and problem-solving abilities, with a demonstrated capacity to learn and apply new technical concepts.
  • Effective communication and teamwork skills, with the ability to collaborate in a multidisciplinary environment.
  • A proactive attitude toward continues learning, with enthusiasm for exploring emerging technologies in CAD and EDA domains.

Expected Base Pay Range (USD)

27 - 55, $ per hour.

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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